Specialized components engineered to withstand harsh chemical, thermal, or mechanical industrial environments.
| Milestone | Target Date | Expected Enhancement | |-----------|-------------|----------------------| | (Second‑generation ASIC) | Q4 2026 | 30 % lower power, integrated on‑chip PLL. | | Multi‑Lane Scaling (×8) | H1 2027 | Aggregate bandwidth > 1.5 Tbps, targeted at large‑scale quantum simulators. | | Integrated Cryogenic Photonic Modulator | H2 2027 | Direct on‑chip conversion from microwave to optical, removing external converters. | | Standardization | 2028 | Submission of the IEEE 802.3cu‑JUQ draft to the IEEE 802.3 Working Group. | | Open‑Source Firmware | 2028 | Release of fully open firmware for the driver ASIC under BSD‑3‑Clause. |
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| Partner | Contribution | |---------|--------------| | | Early adopter; integrated JUQ016 into the IBM Quantum System Two for inter‑module QEC. | | Rigetti | Co‑development of the cryogenic driver ASIC, leveraging their 7 nm RF process. | | Google Quantum AI | Benchmarked JUQ016 against proprietary interconnects; reported 2× speed‑up in Sycamore‑style experiments. | | Intel | Provided the SiN waveguide platform for the optical mode and contributed the Silicon‑Photonic Integration Kit (SPIK). | | University of Sydney | Conducted independent latency measurement campaign; results published in Nature Quantum Electronics (2026). |