Rtl9210b Datasheet

(5 pts) The datasheet recommends a controlled-impedance differential pair of 90 Ω ±10% for high-speed lanes. Describe how stack-up selection, trace width/spacing, and dielectric thickness influence impedance. Provide numerical example: for a 4-layer FR-4 stack-up with core dielectric thickness 0.2 mm and dielectric constant 4.2, estimate trace width to achieve ~45 Ω single-ended (i.e., 90 Ω diff). (Approximate formulas acceptable; state assumptions.)

: USB 3.2 Gen 2 (up to 10 Gbps transfer rate). Backward compatible with USB 3.2 Gen 1 (5 Gbps), USB 2.0, and USB 1.1. Device Interface : rtl9210b datasheet

(6 pts) For an I2C control interface specified at 1.8 V logic, the datasheet gives pin leakage and pull-up current recommendations. Calculate required pull-up resistor value to achieve a valid logic-high within 200 ns on a bus capacitance of 100 pF. Assume CMOS input threshold = 0.7 * VDD and ignore line driver resistance. Show steps. (Approximate formulas acceptable; state assumptions